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RT8153C/d 1 ds8153c/d-05 april 2011 www.richtek.com single phase pwm controller for cpu core power supply general description the RT8153C/d is a single phase pwm controller with integrated mosfet drivers. moreover, it is compliant with intel imvp6.5 voltage regulator specification to fulfill its mobile cpu core and render core voltage regulator requirements. the RT8153C/d adopts g-navp (green native avp), which is a richtek proprietary topology derived from finite dc gain compensator constant on-time mode, making it an easy setting pwm controller which meets all intel avp (active voltage positioning) mobile cpu/render requirements. the output voltage of the RT8153C/d is set by a 7-bit vid code. the built in high accuracy dac converts the vid code into a voltage ranging from 0v to 1.5v with 12.5mv per step. the system accuracy of the controller can reach 1.5%. the part supports vid on the fly and mode change on the fly functions that are fully compliant with imvp6.5 specification. it operates in single phase and diode emulation modes. it can reach up to 90% efficiency in different modes according to different loading conditions. the RT8153C/d includes power good and thermal throttling indicator and an additional clock enabling for cpu core specification. the soft-start and output transition slew rate is programmable by an external capacitor. it also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and thermal shutdown. the RT8153C/d is available in wqfn-32l 5x5 and wqfn-32l 4x4 small foot print packages. features z z z z z single phase pwm controller with integrated mosfet driver z z z z z g-navp tm control topology z z z z z 7-bit dac with 0.8% dac accuracy z z z z z 1.5% or 11.5mv system accuracy z z z z z fixed v boot 1.1v (only for RT8153C cpu core only) z z z z z fixed v boot 1.2v (only for rt8153d cpu core only) z z z z z current monitor output z z z z z built-in offset programming for platform z z z z z differential remote voltage sensing z z z z z diode emulation mode at light load condition z z z z z programmable output transition slew rate control z z z z z system thermal compensated avp z z z z z fast transient response z z z z z load line enable/disable z z z z z power good indicator z z z z z clock enable output (for cpu core only) z z z z z thermal throttling z z z z z switching frequency up to 1mhz z z z z z ovp, uvp, ocp, otp, uvlo, nvp z z z z z rohs compliant and halogen free applications z imvp 6.5 v core /render z avp step-down converter z notebook / desktop computer / servers note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ordering information package type qw : wqfn-32l 5x5 (w-type) qw : wqfn-32l 4x4 (w-type) lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free) RT8153C/d v boot c : 1.1v d : 1.2v package size l : 5x5 s : 4x4
RT8153C/d 2 ds8153c/d-05 april 2011 www.richtek.com pin configurations (top view) wqfn-32l 5x5 / wqfn-32l 4x4 marking information ntc boot pgood clken vcc soft dprslpvr lgate ton ofs pvdd pgnd phase ugate vid6 vid1 vid0 vid3 vid4 vid5 isen cmset rgnd cm vsen fb comp isen_n vron 1 2 3 4 5 6 7 21 20 19 18 17 16 15 8 9101112 14 13 28 27 26 25 24 22 23 32 31 30 29 gnd 33 ocset vid2 vrtt RT8153Clzqw : product number ymdnn : date code RT8153Clgqw rt8153dlzqw : product number ymdnn : date code rt8153dlgqw eh= : product code ymdnn : date code RT8153Csgqw ej= : product code ymdnn : date code rt8153dsgqw RT8153Clzqw rt8153dlzqw eh=ym dnn eh : product code ymdnn : date code RT8153Cszqw ej=ym dnn ej : product code ymdnn : date code rt8153dszqw RT8153Clgqw : product number ymdnn : date code rt8153dlgqw : product number ymdnn : date code rt8153dl zqw ymdnn RT8153Cl zqw ymdnn eh ym dnn ej ym dnn RT8153Cl gqw ymdnn rt8153dl gqw ymdnn
RT8153C/d 3 ds8153c/d-05 april 2011 www.richtek.com typical application circuit figure 1. imvp 6.5 cpu core application circuit v o u t v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 5 v 2 9 2 3 2 2 2 0 2 7 2 8 2 1 1 5 5 2 v i d 0 v i d 1 v i d 2 v i d 3 u g a t e i s e n _ n r t 8 1 5 3 c / d v i d 4 l g a t e p g n d 3 1 3 0 p v d d 2 4 1 7 v c c r g n d b o o t p g o o d 7 p h a s e o c s e t i s e n 1 6 r 1 1 p w r g d 3 . 3 v l 1 v i n c 5 r 7 c 7 c 1 r 1 c 4 q 1 q 2 r 4 r 5 r 8 5 v t o 2 5 v r 6 * c 6 * d 1 * c o u t c m s e t 1 1 1 2 c o m p 1 4 v s e n r 1 8 r 1 9 c 1 3 c 1 2 c 1 0 s o f t 8 9 r 1 7 r 1 6 r 1 5 n t c 2 v c c c p u v s s _ s e n s e d p r s l p v r 3 d p r s l p v r o f s 18 c 9 1 9 c 2 c 3 t o n r 2 r 3 v i d 5 v i d 6 2 5 2 6 v i d 5 v i d 6 r 1 3 1 3 f b c m r 1 2 c 1 1 c m 1 0 vrtt 32 r 9 v c c p vrtt r 2 3 1 n t c v r o n 4 v r o n r 2 1 c p u v c c _ s e n s e r 2 2 33 (exposed pad) g n d * = o p t i o n a l 6 c l k e n r 1 0 c l k e n r 1 4 r 2 0 n t c 1 v c c r 2 4
RT8153C/d 4 ds8153c/d-05 april 2011 www.richtek.com figure 2. imvp 6.5 cpu core with offset application circuit v o u t v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 5 v 2 9 2 3 2 2 2 0 2 7 2 8 2 1 1 5 5 2 v i d 0 v i d 1 v i d 2 v i d 3 u g a t e i s e n _ n r t 8 1 5 3 c / d v i d 4 l g a t e p g n d 3 1 3 0 p v d d 2 4 1 7 v c c r g n d b o o t p g o o d 7 p h a s e o c s e t i s e n 1 6 r 1 1 p w r g d 3 . 3 v l 1 v i n c 5 r 7 c 7 c 1 r 1 c 4 q 1 q 2 r 4 r 5 r 8 5 v t o 2 5 v r 6 * c 6 * d 1 * c o u t c m s e t 1 1 1 2 c o m p 1 4 v s e n r 1 8 r 1 9 c 1 3 c 1 2 c 1 0 s o f t 8 9 r 1 7 r 1 6 r 1 5 n t c 2 v c c c p u v s s _ s e n s e d p r s l p v r 3 d p r s l p v r o f s 18 c 9 1 9 c 2 c 3 t o n r 2 r 3 v i d 5 v i d 6 2 5 2 6 v i d 5 v i d 6 r 1 3 1 3 f b c m r 1 2 c 1 1 c m 1 0 vrtt 32 r 9 v c c p vrtt r 2 3 1 n t c v r o n 4 v r o n r 2 1 c p u v c c _ s e n s e r 2 2 33 (exposed pad) g n d * = o p t i o n a l 6 c l k e n r 1 0 c l k e n r 1 4 r 2 0 n t c 1 v c c r 2 4 1 v t o 1 . 6 v
RT8153C/d 5 ds8153c/d-05 april 2011 www.richtek.com figure 3. imvp 6.5 render application circuit v o u t v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 5 v 2 9 2 3 2 2 2 0 2 7 2 8 2 1 1 5 5 2 v i d 0 v i d 1 v i d 2 v i d 3 u g a t e i s e n _ n r t 8 1 5 3 c / d v i d 4 l g a t e p g n d 3 1 3 0 p v d d 2 4 1 7 v c c r g n d b o o t p g o o d 7 p h a s e o c s e t i s e n 1 6 r 1 1 p w r g d 3 . 3 v l 1 v i n c 5 r 7 c 7 c 1 r 1 c 4 q 1 q 2 r 4 r 5 r 8 5 v t o 2 5 v r 6 * c 6 * d 1 * c o u t c m s e t 1 1 1 2 c o m p 1 4 v s e n r 1 8 r 1 9 c 1 3 c 1 2 c 1 0 s o f t 8 9 r 1 7 r 1 6 r 1 5 n t c 2 v c c g p u v s s _ s e n s e d p r s l p v r 3 d p r s l p v r o f s 18 c 9 1 9 c 2 c 3 t o n r 2 r 3 v i d 5 v i d 6 2 5 2 6 v i d 5 v i d 6 r 1 3 1 3 f b c m r 1 2 c 1 1 c m 1 0 vrtt 32 r 9 v c c p vrtt r 2 3 1 n t c v r o n 4 v r o n r 2 1 g p u v c c _ s e n s e r 2 2 33 (exposed pad) g n d * = o p t i o n a l 6 c l k e n r 1 4 r 2 0 n t c 1 v c c r 2 4
RT8153C/d 6 ds8153c/d-05 april 2011 www.richtek.com figure 4. imvp 6.5 render with offset application circuit v o u t v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 5 v 2 9 2 3 2 2 2 0 2 7 2 8 2 1 1 5 5 2 v i d 0 v i d 1 v i d 2 v i d 3 u g a t e i s e n _ n r t 8 1 5 3 c / d v i d 4 l g a t e p g n d 3 1 3 0 p v d d 2 4 1 7 v c c r g n d b o o t p g o o d 7 p h a s e o c s e t i s e n 1 6 r 1 1 p w r g d 3 . 3 v l 1 v i n c 5 r 7 c 7 c 1 r 1 c 4 q 1 q 2 r 4 r 5 r 8 5 v t o 2 5 v r 6 * c 6 * d 1 * c o u t c m s e t 1 1 1 2 c o m p 1 4 v s e n r 1 8 r 1 9 c 1 3 c 1 2 c 1 0 s o f t 8 9 r 1 7 r 1 6 r 1 5 n t c 2 v c c g p u v s s _ s e n s e d p r s l p v r 3 d p r s l p v r 18 c 9 1 9 c 2 c 3 t o n r 2 r 3 v i d 5 v i d 6 2 5 2 6 v i d 5 v i d 6 r 1 3 1 3 f b c m r 1 2 c 1 1 c m 1 0 vrtt 32 r 9 v c c p vrtt r 2 3 1 n t c v r o n 4 v r o n r 2 1 g p u v c c _ s e n s e r 2 2 33 (exposed pad) g n d * = o p t i o n a l 6 c l k e n r 1 4 r 2 0 n t c 1 v c c r 2 4 1 v t o 1 . 6 v o f s
RT8153C/d 7 ds8153c/d-05 april 2011 www.richtek.com pin no. pin name pin function 1 ntc thermal detection input for vrtt circuit. connect this pin with a resistor divider from v cc using ntc on the top to set the thermal management threshold level. furthermore, this pin provides load line enable/disable function. 2 ocset over current protection setting. connect a resistor voltage divider from v cc to ground, the joint of the resistive voltage divider is connected to the ocset pin, with a voltage v ocset , to set the over current threshold i lim . 3 dprslpvr deeper sleep mode signal. 4 vron voltage regulator enabler. 5 pgood power good indicator. 6 clken inverted clock enable. pull high by a resistor for cpu core application. this open-drain pin is an output indicating the start of the pll locking of the clock chip. connect to gnd for render application. 7 vcc chip power. 8 soft soft-start. this pin provides soft-start function and slew rate controller. the capacitance of the slew rate control capacitor is restricted to be larger than 10nf. the feedback voltage of the converter follows the ramping voltage on the soft pin during soft-start and other voltage transitions according to different mode of operation and vid change. 9 rgnd return ground. this pin is the negative node of the differential remote voltage sensing. 10 cm current monitor output. this pin outputs a voltage proportional to the output current. 11 c ms e t current monitor output gain externally setting. connect this pin with one resistor to vsen the while cm pin is connected to ground with another resistor. in such a way, the current monitor output gain can be set by the ratio of these two resistors. 12 vsen positive voltage sensing pin. this pin is the positive node of the differential voltage sensing. 13 fb feedback. this is the negative input node of the error amplifier. 14 comp compensation pin. this pin is the output node of the error amplifier. 15 isen_n negative input of the current sense. 16 isen positive input of the current sense. 17 ton connect this pin to v in with one resistor. 18 ofs output voltage offset setting. 19 pvdd driver power. 20 lgate lower gate drive. this pin drives the gate of the low side mosfets. 21 pgnd driver ground. 22 phase this pin is the return node of the high side mosfet driver. connect this pin to the high side mosfet sources together with the low side mosfet drains and the inductor. 23 ugate upper gate drive. this pin drives the gate of the high side mosfets. 24 boot bootstrap power pin. this pin powers the high side mosfet drivers. connect this pin to bootstrap capacitor. functional pin description to be continued
RT8153C/d 8 ds8153c/d-05 april 2011 www.richtek.com function block diagram pin no. pin name pin function 25 to 31 vid6 to vid0 voltage id. dac voltage identification inputs for imvp6.5. the logic threshold is 30% of vcc as the maximum value for low state and 70% of the vcc as the minimum value for the high state. 32 vrtt voltage regulator thermal throttling. this open drain output pin will be pulled low when the preset temperature level is exceeded. 33 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. comp rgnd ofs ovp trip point vid1 vid3 vid4 vid5 vid0 vid2 fb pgood vcc gnd error amp ocp setting soft start/slew rate control/offset control nvp trip point power on reset & central logic vsen vron ocset ntc vid6 mode selection dprslpvr 1.1v for RT8153C 1.2v for rt8153d uvp trip point otp + - vcc mux dac + - + - + - + - + - isen_n pwmcp driver logic control pgnd lgate pvdd phase ugate boot isen cm - + - + 10 c l k e n v r t t cm cmset power saving mode ton offset cancellation + - soft 0ll soft 0ll dprslpvr 2v
RT8153C/d 9 ds8153c/d-05 april 2011 www.richtek.com vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 0 0 0 0 0 0 1.5000v 0 0 0 0 0 0 1 1.4875v 0 0 0 0 0 1 0 1.4750v 0 0 0 0 0 1 1 1.4625v 0 0 0 0 1 0 0 1.4500v 0 0 0 0 1 0 1 1.4375v 0 0 0 0 1 1 0 1.4250v 0 0 0 0 1 1 1 1.4125v 0 0 0 1 0 0 0 1.4000v 0 0 0 1 0 0 1 1.3875v 0 0 0 1 0 1 0 1.3750v 0 0 0 1 0 1 1 1.3625v 0 0 0 1 1 0 0 1.3500v 0 0 0 1 1 0 1 1.3375v 0 0 0 1 1 1 0 1.3250v 0 0 0 1 1 1 1 1.3125v 0 0 1 0 0 0 0 1.3000v 0 0 1 0 0 0 1 1.2875v 0 0 1 0 0 1 0 1.2750v 0 0 1 0 0 1 1 1.2625v 0 0 1 0 1 0 0 1.2500v 0 0 1 0 1 0 1 1.2375v 0 0 1 0 1 1 0 1.2250v 0 0 1 0 1 1 1 1.2125v 0 0 1 1 0 0 0 1.2000v 0 0 1 1 0 0 1 1.1875v 0 0 1 1 0 1 0 1.1750v 0 0 1 1 0 1 1 1.1625v 0 0 1 1 1 0 0 1.1500v 0 0 1 1 1 0 1 1.1375v 0 0 1 1 1 1 0 1.1250v 0 0 1 1 1 1 1 1.1125v 0 1 0 0 0 0 0 1.1000v table 1. imvp6.5 vid code table vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 1 0 0 0 0 1 1.0875v 0 1 0 0 0 1 0 1.0750v 0 1 0 0 0 1 1 1.0625v 0 1 0 0 1 0 0 1.0500v 0 1 0 0 1 0 1 1.0375v 0 1 0 0 1 1 0 1.0250v 0 1 0 0 1 1 1 1.0125v 0 1 0 1 0 0 0 1.0000v 0 1 0 1 0 0 1 0.9875v 0 1 0 1 0 1 0 0.9750v 0 1 0 1 0 1 1 0.9625v 0 1 0 1 1 0 0 0.9500v 0 1 0 1 1 0 1 0.9375v 0 1 0 1 1 1 0 0.9250v 0 1 0 1 1 1 1 0.9125v 0 1 1 0 0 0 0 0.9000v 0 1 1 0 0 0 1 0.8875v 0 1 1 0 0 1 0 0.8750v 0 1 1 0 0 1 1 0.8625v 0 1 1 0 1 0 0 0.8500v 0 1 1 0 1 0 1 0.8375v 0 1 1 0 1 1 0 0.8250v 0 1 1 0 1 1 1 0.8125v 0 1 1 1 0 0 0 0.8000v 0 1 1 1 0 0 1 0.7875v 0 1 1 1 0 1 0 0.7750v 0 1 1 1 0 1 1 0.7625v 0 1 1 1 1 0 0 0.7500v 0 1 1 1 1 0 1 0.7375v 0 1 1 1 1 1 0 0.7250v 0 1 1 1 1 1 1 0.7125v 1 0 0 0 0 0 0 0.7000v 1 0 0 0 0 0 1 0.6875v to be continued
RT8153C/d 10 ds8153c/d-05 april 2011 www.richtek.com vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 0 0 0 0 1 0 0.6750v 1 0 0 0 0 1 1 0.6625v 1 0 0 0 1 0 0 0.6500v 1 0 0 0 1 0 1 0.6375v 1 0 0 0 1 1 0 0.6250v 1 0 0 0 1 1 1 0.6125v 1 0 0 1 0 0 0 0.6000v 1 0 0 1 0 0 1 0.5875v 1 0 0 1 0 1 0 0.5750v 1 0 0 1 0 1 1 0.5625v 1 0 0 1 1 0 0 0.5500v 1 0 0 1 1 0 1 0.5375v 1 0 0 1 1 1 0 0.5250v 1 0 0 1 1 1 1 0.5125v 1 0 1 0 0 0 0 0.5000v 1 0 1 0 0 0 1 0.4875v 1 0 1 0 0 1 0 0.4750v 1 0 1 0 0 1 1 0.4625v 1 0 1 0 1 0 0 0.4500v 1 0 1 0 1 0 1 0.4375v 1 0 1 0 1 1 0 0.4250v 1 0 1 0 1 1 1 0.4125v 1 0 1 1 0 0 0 0.4000v 1 0 1 1 0 0 1 0.3875v 1 0 1 1 0 1 0 0.3750v 1 0 1 1 0 1 1 0.3625v 1 0 1 1 1 0 0 0.3500v 1 0 1 1 1 0 1 0.3375v 1 0 1 1 1 1 0 0.3250v 1 0 1 1 1 1 1 0.3125v 1 1 0 0 0 0 0 0.3000v vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 1 0 0 0 0 1 0.2875v 1 1 0 0 0 1 0 0.2750v 1 1 0 0 0 1 1 0.2625v 1 1 0 0 1 0 0 0.2500v 1 1 0 0 1 0 1 0.2375v 1 1 0 0 1 1 0 0.2250v 1 1 0 0 1 1 1 0.2125v 1 1 0 1 0 0 0 0.2000v 1 1 0 1 0 0 1 0.1875v 1 1 0 1 0 1 0 0.1750v 1 1 0 1 0 1 1 0.1625v 1 1 0 1 1 0 0 0.1500v 1 1 0 1 1 0 1 0.1375v 1 1 0 1 1 1 0 0.1250v 1 1 0 1 1 1 1 0.1125v 1 1 1 0 0 0 0 0.1000v 1 1 1 0 0 0 1 0.0875v 1 1 1 0 0 1 0 0.0750v 1 1 1 0 0 1 1 0.0625v 1 1 1 0 1 0 0 0.0500v 1 1 1 0 1 0 1 0.0375v 1 1 1 0 1 1 0 0.0250v 1 1 1 0 1 1 1 0.0125v 1 1 1 1 0 0 0 0.0000v 1 1 1 1 0 0 1 0.0000v 1 1 1 1 0 1 0 0.0000v 1 1 1 1 0 1 1 0.0000v 1 1 1 1 1 0 0 0.0000v 1 1 1 1 1 0 1 0.0000v 1 1 1 1 1 1 0 0.0000v 1 1 1 1 1 1 1 0.0000v
RT8153C/d 11 ds8153c/d-05 april 2011 www.richtek.com recommended operating conditions (note 4) z supply voltage, v cc --------------------------------------------------------------------------------------------- 4.5v to 5.5v z battery voltage, v in --------------------------------------------------------------------------------------------- 5v to 25v z junction temperature range ----------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ----------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z v cc to gnd -------------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z rgnd, pgnd to gnd ------------------------------------------------------------------------------------------- ? 0.3v to 0.3v z vidx to gnd ------------------------------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z dprslpvr, vron to gnd ----------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z pgood, clken, vrtt to gnd ------------------------------------------------------------------------------ ? 0.3v to (v cc + 0.3v) z vsen, fb, comp, soft, ocset, cm, cmset, ntc to gnd --------------------------------------- ? 0.3v to (v cc + 0.3v) z isen, isen_n to gnd ------------------------------------------------------------------------------------------ ? 0.3v to (v cc + 0.3v) z pvdd to pgnd --------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z lgate to pgnd dc -------------------------------------------------------------------------------------------------------------------- ? 0.3v to (pvdd + 0.3v) <20ns --------------------------------------------------------------------------------------------------------------- ? 2.5v to 7.5v z phase to pgnd dc -------------------------------------------------------------------------------------------------------------------- ? 0.3v to 30v <20ns --------------------------------------------------------------------------------------------------------------- ? 8v to 38v z boot to phase ------------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z ugate to phase dc -------------------------------------------------------------------------------------------------------------------- ? 0.3v to (pvdd + 0.3v) <20ns --------------------------------------------------------------------------------------------------------------- ? 5v to 7.5v z ton to gnd ------------------------------------------------------------------------------------------------------- ? 0.3v to 30v z power dissipation, p d @ t a = 25 c wqfn ? 32l 5x5 --------------------------------------------------------------------------------------------------- 2.778w wqfn ? 32l 4x4 --------------------------------------------------------------------------------------------------- 1.923w z package thermal resistance (note 2) wqfn ? 32l 5x5, ja --------------------------------------------------------------------------------------------- 36 c/w wqfn ? 32l 5x5, jc --------------------------------------------------------------------------------------------- 6 c/w wqfn ? 32l 4x4, ja --------------------------------------------------------------------------------------------- 52 c/w wqfn ? 32l 4x4, jc --------------------------------------------------------------------------------------------- 7 c/w z junction temperature -------------------------------------------------------------------------------------------- 150 c z storage temperature range ----------------------------------------------------------------------------------- ? 65 c to 150 c z lead temperature (soldering, 10 sec.) -- -------------------------------------------------------------------- 260 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------------------- 2kv mm (ma chine mode) --------------------------------------------------------------------------------------------- 200v
RT8153C/d 12 ds8153c/d-05 april 2011 www.richtek.com to be continued electrical characteristics (v cc = 5v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit ofs function (only for RT8153C/d) enable offset v ofs > 0.92v before vron rising ofs threshold voltage disable offset v ofs connected to gnd before vron ri sing 0.92 1.2 -- v no offset voltage -- 1.2 -- offset 400mv -- 1.6 -- set ofs voltage v ofs offset ? 200mv -- 1 -- v impedance r ofs 1 -- -- m oll function i 0ll pulse sinking current source ntc resistor at vron rising edge. -- 80 -- a ntc v 0ll detect and latch voltage at ntc pin at vron rising edge. v ntc < v 0ll , enable 0 load line function. 2 -- -- v supply input supply voltage v cc 4.5 5 5.5 v supply current i vcc + i pvcc v ron = 3.3v, not switching -- -- 10 ma shutdown current i cc + i pvcc v ron = 0v -- -- 5 a soft-start/slew rate control (based on 10nf c ss ) soft-start / soft-shutdown i ss1 v soft = 1.5v -- 20 -- a normal vid change slew current i ss2 v soft = 1.5v 40 50 60 a deeper sleep exit/vid change slew current (only at imvp6.5 render application) i ss3 v soft = 1.5v 80 100 120 a reference and dac v vid = 0.7500 ? 1.5000 (no load, active mode ) ? 0.5 0 0.5 %vid dc accuracy v fb v vid = 0.5000 ? 0.7500 ? 7.5 0 7.5 mv for RT8153C vcore 1.089 1.1 1.111 boot voltage v boot for rt8153d vcore 1.188 1.2 1.212 v error amplifier input offset voltage v osea ? 2 -- 2 mv dc gain r l = 47k 70 80 -- db gain bandwidth product gbw c load = 5pf -- 10 -- mhz slew rate sr comp c load = 10pf (gain = ? 4, r f = 47k , v out = 0.5v ? 3v ) -- 5 -- v/ s output voltage range v comp r l = 47k 0.5 -- 3.6 v
RT8153C/d 13 ds8153c/d-05 april 2011 www.richtek.com parameter symbol test conditions min typ max unit maximum source current v comp = 2v 200 250 -- a maximum sink current i outea_comp v comp = 2v 20 -- -- ma current sense amplifier input offset voltage v oscs ? 1 -- 1 mv impedance at neg. input r isen_n 1 -- -- m impedance at pos input r isen 1 -- -- m dc gain 1 phase operating -- 10 -- v/v v isen linearity v isen_acc ? 30mv < i sen_in < 50mv ? 1 1 % dem ton setting ton pin output voltage v ton i ton = 80 a, v ton = v vid = 0.75 ? 5 0 5 % dem on-time setting t on i rton = 80 a -- 350 -- ns r ton current range i rton 25 -- 280 a protection under voltage lock out threshold v uvlo falling edge. 4.1 4.3 4.5 v uvlo hysteresis -- 200 -- mv absolute over voltage protection threshold v ovabs (respect to 1.7v, 50mv) 1.65 1.7 1.75 v absolute over voltage offset v ovabs_ofs (respect to 2v, 50mv) 1.95 2 2.05 v relative over voltage protection threshold v ov (respect to v dac , 50mv) 250 300 350 mv under voltage protec ti on threshold v uv measured at vsen with respect to unloaded output voltage (uov) (for 0.8 < uov < 1.5) ? 450 ? 400 ? 350 mv negative voltage protection threshold v nv measured at vsen with respect to gnd ? 100 -- -- mv current limit threshold voltage v ilimit v isen ? v isen_n = v ilim , v ocset = 2.4v, 48 x v ilimt = v ocset 45 50 55 mv thermal shut down threshold t sd -- 160 -- c thermal shut down hysteresis t sd -- 10 -- c logic inputs v ih respect to 1.05v, 70% 0.735 -- -- vron threshold v il respect to 1.05v, 30% -- -- 0.315 v leakage current of vron ? 1 -- 1 a v ih respect to 1.05v, 70% 0.735 -- -- dac (vid0 to vid6) and dprslpvr v il respect to 1.05v, 30% -- -- 0.315 v leakage current of dac (vid0 to vid6), psi and dprslpvr ? 1 -- 1 a to be continued
RT8153C/d 14 ds8153c/d-05 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layers test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit power good pgood low voltage v pgood i pgood = 4ma -- -- 0.4 v pgood delay t pgd clk_en low to pgood high 3 -- 20 ms clock enable clken low voltage v clken i clken = 4ma (only for v core ) -- -- 0.4 v thermal throttling thermal throttling threshold v ot measure at ntc respect to v cc -- 80 -- %vdd thermal throttling threshold hysteresis v ot_hy at v cc = 5v -- 230 -- mv vrtt output voltage v vrtt i vrtt = ? 40ma -- -- 0.4 v current monitor current monitor output voltage in operating range v isen ? v isen_n = 20mv, r cm = 18k , r cmset = 12k 450 480 510 mv current monitor maximum output voltage -- -- 1.15 v gate driver upper driver source r ugatesr v boot ? v phase = 5v v boot ? v lgate = 1v -- 1 -- upper driver sink r ugatesk v ugate = 1v 1 lower driver source r lgatesr v pvdd = 5v, v pvdd ? v lgate = 1v -- 1 -- lower driver sink r lgatesk v lgate = 1v -- 0.5 -- upper driver source/sink current i ugate v boot ? v phase = 5v v ugate = 2.5v -- 2 -- a lower driver source current i lgatesr v lgate = 2.5v -- 2 -- a lower driver sink current i lgatesk v lgate = 2.5v -- 4 -- a internal boot charging switch on resistance r boot pvdd to boot -- 30 --
RT8153C/d 15 ds8153c/d-05 april 2011 www.richtek.com typical operating characteristics ccm efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 load current (a) efficiency (%) v in = 8v v in = 12v v in = 19v vid = 1.15v, r ton = 120k , dprslpvr = gnd ccm efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 load current (a) efficiency (%) v in = 8v v in = 12v v in = 19v vid = 0.9375v, r ton = 120k , dprslpvr = gnd dem efficiency vs. load current 50 55 60 65 70 75 80 85 90 0 0.5 1 1.5 2 2.5 3 load current (a) efficiency (%) v in = 8v v in = 12v v in = 19v vid = 0.85v, r ton = 120k , dprslpvr = high ccm v cc_sense vs. load current 0.82 0.84 0.86 0.88 0.90 0.92 0.94 0 5 10 15 20 25 30 load current (a) v cc_sense (v) v in = 8v v in = 12v v in = 19v vid = 0.9375v, r ton = 120k , dprslpvr = gnd v cm vs. load current 0 200 400 600 800 1000 1200 0 5 10 15 20 25 30 load current (a) v cm (mv) v in = 8v v in = 12v v in = 19v vid = 0.9375v, r ton = 120k , dprslpvr = gnd ccm v cc_sense vs. load current 1.04 1.06 1.08 1.10 1.12 1.14 1.16 0 5 10 15 20 25 30 load current (a) v cc_sense (v) v in = 8v v in = 12v v in = 19v vid = 1.15v, r ton = 120k , dprslpvr = gnd
RT8153C/d 16 ds8153c/d-05 april 2011 www.richtek.com ccm vid change down v cc_sense (100mv/div) time (20 s/div) ugate (20v/div) lgate (5v/div) vid change from 0.9375v to 0.85v vid0 (2v/div) v in = 12v, dprslpvr = gnd, no load cpu mode power down v cc_sense (1v/div) time (100 s/div) pgood (5v/div) vron (5v/div) vid = 0.9375v, clken pull high to 3.3v clken (5v/div) ccm vid change up v cc_sense (100mv/div) time (20 s/div) ugate (20v/div) lgate (5v/div) vid change from 0.85v to 0.9375v vid0 (2v/div) v in = 12v, dprslpvr = gnd, no load cpu-dem vid change down v cc_sense (100mv/div) time (20 s/div) ugate (20v/div) lgate (5v/div) v in = 12v, dprslpvr = high, no load vid0 (2v/div) vid change from 0.9375v to 0.85v render mode power on v cc_sense (1v/div) time (1ms/div) pgood (5v/div) vron (5v/div) clken (5v/div) vid = 0.9375v, clken pull low to gnd cpu mode power on v cc_sense (1v/div) time (1ms/div) pgood (5v/div) vron (5v/div) clken (5v/div) vid = 0.9375v, clken pull high to 3.3v
RT8153C/d 17 ds8153c/d-05 april 2011 www.richtek.com under voltage protection v cc_sense (1v/div) time (10 s/div) lgate (5v/div) pgood (2v/div) vin = 12v, vid = 0.9375, v dprslpvr = gnd ugate (20v/div) ccm load transient response v cc_sense (100mv/div) time (10 s/div) ugate (20v/div) lgate (5v/div) dprslpvr = gnd v in = 12v, vid = 0.9375v, i load = 5a to 28a over current protection v cc_sense (1v/div) time (10 s/div) phase (10v/div) pgood (2v/div) i load (20a/div) v in = 12v, vid = 0.9375v, dprslpvr = gnd over voltage protection v cc_sense (1v/div) time (10 s/div) lgate (10v/div) pgood (2v/div) v in = 12v, vid = 0.9375v, dprslpvr = gnd ugate (20v/div) ccm load transient response v cc_sense (100mv/div) time (10 s/div) ugate (20v/div) lgate (5v/div) v in = 12v, vid = 0.9375v, i load = 28a to 5a dpslpvr = high
RT8153C/d 18 ds8153c/d-05 april 2011 www.richtek.com application information the RT8153C/d is a single-phase pwm controller with embedded gate driver. it is compliant with intel imvp6.5 voltage regulator specification to fulfill its mobile cpu and render voltage regulator power supply requirement. inductor current are continuously sensed for loop control, droop tuning, and over current protection. the 7-bit vid dac and low offset differential amplifier allow the controller to maintain high regulating accuracy to meet intel?s imvp6.5 specification. design tool to help users to reduce the efforts and errors caused by manual calculations using the design concept below, a user-friendly design tool is now available on request. this design tool calculates all necessary design parameters by entering user's requirements. please contact richtek's representatives for details. operation modes table 2 shows the RT8153C/d operation modes. when vron is enabled (=1), the RT8153C/d will detect clken within 10 s to determine which operation mode is applied. if clken is low, the RT8153C/d will operate in render core voltage regulator mode. if clken is high, the ic will operate in cpu core voltage regulator mode. dprslpvr determines whether the operation mode of the controller operation is in ccm or dem. the controller enters dem (diode emulation mode) when dprslpvr = 1 and enters ccm when dprslpvr = 0. table 2. control signal truth table for operation modes of the RT8153C/d clken dprslpvr operation mode 0 render ccm 0 (gnd) 1 render dem 0 cpu ccm 1 (pul l high) 1 cpu dem differential remote sense connection the RT8153C/d includes differential, remote-sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes, and socket contacts. cpu contains on-die sense pins v cc_sense and v ss_sense . connect rgnd to v ss_sense . connect fb to v cc_sense with a resistor to build the negative input path of the error amplifier. connect vsen to v cc_sense for clken, pgood, ovp, and uvp detection. the 7 bit vid dac and the precision voltage reference are referred to rgnd for accurate remote sensing. current sense setting the RT8153C/d is continuously sensing the inductor current. therefore, the controller can be less noise sensitive. low offset amplifiers are used for loop control and over current detection. the internal current sense amplifier gain (a i ) is fixed to be 10. isen and isen_n denote the positive and negative inputs of the current sense amplifier. users can either use a current-sense resistor or the inductor's dcr for current sensing. using inductor's dcr allows higher efficiency as shown in figure 5. if x x l rc dcr = (1) == ? x 0.36 h r3.6k 1m 1 0 0 n f (2) then the transient performance will be optimum. for example, choose l = 0.36 h with 1m dcr and c x = 100nf, to yield for r x : figure 5. lossless inductor current sensing phase isen isen_n v out l dcr r x c x + v x -
RT8153C/d 19 ds8153c/d-05 april 2011 www.richtek.com considering the inductance tolerance, the resistor, r x , has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, r x is chosen too small. vice-versa, with a resistance too large, the output voltage transient has only a small initial dip and the recovery become too fast, causing a ring-back. since the dcr of inductor is highly temperature dependent, it affects the output accuracy, current monitor and over current protection accuracy at hot conditions. temperature compensation is recommended for the lossless inductor dcr current sense method. figure 6 shows a simple but effective way of compensating the temperature variations of the sense resistor using an ntc thermistor at dcr sensing network. figure 6. lossless inductor current sensing with ntc compensation usually, r p is set to equal r ntc (25 c). r s is selected to linearize the ntc's temperature characteristic. for a given ntc, design is to get r s and r x to compensate the temperature variations of the sense resistor. let =+ equ s p ntc rr(r//r) (3) then, according to above circuit, = + equ x xequ r l c x dcr r r (4) next, let = x l m dcr x c (5) + ???? ++ =+ ???? ++ ???? ntc p ntc p xs x s ntcp ntcp rr r r mr r r r rr rr then (6) so ?+ ? = ?? + + ntc p x ntc p x ntc p s ntc p x ntc p r r r (mr mr )r mr r r (r r)r m(r r) (7) r x can be expressed by : ? ? = 2 x bb4ac r 2a (8) where a = a th c tl ? a tl c th b = a th d tl ? b tl c th ? a tl d th c = b tl d th ? b th d tl where a th = r ntc_th r p ? m th r ntc_th ? m th r p a tl = r ntc_tl r p ? m tl r ntc_tl ? m tl r p b th = r ntc_th r p b tl = r ntc_tl r p c th = ? r ntc_th ? r p c tl = ? r ntc_tl ? r p d th = m th (r ntc_th + r p ) d tl = m tl (r ntc_tl + r p ) where x th denotes the value of this variable at high temperature, and x tl denotes the value of this variable at low temperature. using current sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. considering the equivalent inductance (l esl ) of the current sense resistor, a rc filter is recommended. the rc filter calculation method is similar to the above-mentioned inductor dcr sensing method. loop control the RT8153C/d adopts richtek's proprietary g-navp tm topology. g-navp tm is based on the finite-gain current mode with ccrcot (constant current ripple constant on time) topology. the output voltage, v out , will decrease with increasing output load current. the control loop consists of pwm modulator with power stage, current sense amplifier and error amplifier as shown in figure 7. phase isen isen_n l dcr v out r x c x r p r s r ntc
RT8153C/d 20 ds8153c/d-05 april 2011 www.richtek.com where a i is the internal current sense amplifier gain. r sense is the current sense resistor. if no external sense resistor present, it is the dcr of the inductor. r droop is the resistive slope value of the converter output and is the desired static output impedance. figure 8. error amplifier gain (a v ) influence on v out figure 7. simplified schematic for droop and remote sense in ccm the hs_fet on-time is determined by ccrcot on-time generator. when load current increases, v cs increases, the steady-state comp voltage also increases and makes v out decrease, achieving avp. a near-dc offset cancellation is added to the output of ea to cancel the inherent output offset of finite-gain current mode controller. in rfm, hs_fet is turned on with constant t on when v cs is lower than v comp2 . once hs_fet is turned off, ls_fet is turned on automatically. with ringing-free technique, ls_fet allows only partial negative current when the inductor free-wheeling current reaches negative. the switching frequency will be proportionately reduced, thus the conduction and switching losses will be greatly reduced. output voltage droop setting (with temperature compensation) it's very easy to achieve active voltage positioning (avp) by properly setting the error amplifier gain due to the native droop characteristics. the target is to have v out = v dac ? i load x r droop (9) , then solving the switching condition v comp = v cs in figure 7 yields the desired error amplifier gain as i sense v droop ar r2 a r1 r == (10) a v1 a v2 a v2 > a v1 v out load current 0 as shown in figure 9, when dcr sensing network is used for ntc thermistor temperature compensation, the error amplifier gain can be calculated as : == i sense v droop ar z2 ak z1 r where k is the dividing ratio of dcr sensing as shown below : = + z2 k z1 z2 phase isen isen_n ldcr v out c x z1 z2 figure 9. using an ntc thermistor at dcr sensing network loop compensation optimized compensation of the RT8153C/d allows for best possible load step response of the regulator's output. a compensator with one pole and one zero is adequate for a proper compensation. figure 7 shows the compensation circuit. prior design procedure shows how to determine (11) (12) v out ccrcot pwm logic ugate lgate + - isen isen_n a i + - cmp v cs comp2 v in RT8153C/d hs_fet ls_fet l r x c x c ea v cc_sense - + v ss_sense fb soft rgnd comp c2 c1 r2 r1 c soft v dac + - offset cancellation 10nf
RT8153C/d 21 ds8153c/d-05 april 2011 www.richtek.com = ? ?? + +? ?? ?? + ? ?? s(max) on hs-delay dac(max) load(max) on _ ls-fet l droop in(max) load(max) on _ ls-fet on _ hs-fet 1 f tt vi r dcrr vi r r p c 1 f 2cr = (13) where c is the capacitance of output capacitor and r c is the esr of output capacitor. c2 can be calculated as follows : c cr c2 r2 = (14) the zero of compensator has to be placed at half of the switching frequency to filter the switching-related noise, such that, (15) () ntc, 25 sw 1 c1 r1b r1a // r f = + ton setting high frequency operation optimizes the application for the smaller component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at the expense of component size and board space. figure 10 shows the on-time setting circuit. connect a resistor (r ton ) between vin and ton to set the on-time of ugate: the resistive feedback components of error amplifier gain. the c1 and c2 must be calculated for the compensation. the target is to achieve constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : (16) ? = ? 12 ton on in dac 14.5 10 r 2 t (v v ) where t on is ugate turn on period, v in is input voltage of converter, v dac is dac voltage. on-time translates only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in external hs-fet. also, the dead-time effect increases the effective on-time, reducing the switching frequency. it occurs only in ccm (dprslpvr = 0) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, phase goes high earlier than normal, extending the on- time by a period equal to the hs-fet rising dead time. for better efficiency of the given load range, the maximum switching frequency is suggested to be : (17) where ` fs max is the maximum switching frequency ` t hs- delay is the turn on delay of hs-fet ` v dac(max) is the maximum vdac of application ` v inmax is the maximum application input voltage ` i load(max) is the maximum load of application ` r on_ls-fet is the low side fet r ds(on) ` r on_hs-fet is the high side fet r ds(on) ` dcr l is the inductor dcr ` r droop is the load line setting figure 10. on-time setting with rc filter ccrcot on-time generator ton v in r ton r1 c1 v dac on-time soft-start and mode transition slew rates the RT8153C/d uses 3 slew rates for various modes of operation. the three slew rates are internally determined by commanding one of three bi-directional current sources (i ss ) into the soft pin. the 7 bit vid dac and the precision voltage reference are referred to rgnd for accurate remote sensing. hence, connect a capacitor (c soft ) from soft pin to rgnd for controlling the slew rate as shown in figure 7. the capacitance of capacitor is restricted to be larger than 10nf. the voltage (v soft ) on the soft pin is the reference voltage of the error amplifier and is, therefore, the commanded system voltage. the first current is typically 20 a used to charge or discharge the c soft during soft-start, and soft-shutdown.
RT8153C/d 22 ds8153c/d-05 april 2011 www.richtek.com the second current is typically 50 a used during other voltage transitions, including vid change and transitions between operation modes. the third current is typically 100 a used during render dem with vid change up transitions. the imvp ? 6.5 specification specifies the critical timing associated with regulating the output voltage. the symbol, slewrate, as given in the imvp ? 6.5 specification will determine the choice of the soft capacitor, c soft, by the following equation : (18) ss soft i c slewrate = power up sequence when the controller's vcc voltage rises above the uvlo threshold (typ. 4.3v), the power up sequence begins when vron goes high. if clken = 1 (pull high), the RT8153C/d will enter cpu mode power-up sequence. if clken = 0 (connect to gnd), the controller will enter render mode power up sequence. after the RT8153C/d enters cpu mode, vsen starts ramping up to v boot within 1ms. the slew rate during power-up is 20 a/c soft . the RT8153C/d pulls clken low after vsen gets across v boot ? 0.1v for 73 s. right after clken goes low, vsen starts ramping to first v dac value. after clken goes low for approximately 4.7ms, pgood is asserted high. dprslpvr is valid right after pgood is asserted. uvp is masked as long as vsen is less than v boot ? 0.1v. figure 11. cpu mode timing diagram for power up and power down after the RT8153C/d enters render mode, vsen starts ramping up to vdac within 1ms. the slew rate during power-up is 20 a/c soft . pgood is asserted high after vsen exceeds vdac ? 100mv for 4.77ms (typ.). dprslpvr is valid right after pgood is asserted. uvp is masked as long as vsen is less than vdac ? 100mv. vron vcc 4.3v 4.1v vid valid xx xx vsen pgood 73s typ. 4.7ms typ. uvlo 0.2v v boot v boot - 0.1v dprslpvr valid xx xx pwm dprslpvr defined ccm pull down ccm hi-z clken
RT8153C/d 23 ds8153c/d-05 april 2011 www.richtek.com figure 12. render mode timing diagram for power up and power down vron vcc 4.3v 4.1v vid valid xx xx vsen pgood 4.77ms typ. por 0.2v vdac vdac-100mv dprslpvr valid xx xx pwm dprslpvr defined ccm pull down ccm hi-z power down when vron goes low, the RT8153C/d enters low power shutdown mode. pgood is pulled low immediately and the v soft ramps down with slew rate of 20 a/c soft . vsen also ramps down following v soft . after v vsen is lower than 200mv, the RT8153C/d turns off high side fets and low side fets. an internal discharge resistor at vsen will be enabled and the analog part will be turned off. deeper sleep mode transitions after dprslpvr goes high, the RT8153C/d enters deeper sleep mode operation. if the vids are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. the internal target v soft still ramps as before, and uvp, ocp and ovp are masked for 73 s. over current protection setting the RT8153C/d compares a programmable current limit set point to the voltage from the current sense amplifier output for over current protection (ocp). the voltage applied to ocset pin defines the desired current limit threshold i lim : v ocset = 48 x i lim x r sense (19) connect a resistive voltage divider from vcc to gnd, with (20) cc oc1 oc2 ocset v rr 1 v ?? = ? ?? ?? figure 13. ocp setting without temperature compensation the joint of the voltage divider connected to ocset pin as shown in figure 13. for a given r oc2 , then the RT8153C/d provides current limit function and over current protection. the current limit function is triggered when inductor current exceeds the current limit threshold, i lim , defined by v ocset . when current limit function is tripped, high side mosfet will be forced off until the over current condition is cleared. if the current limit function is triggered for 15 switching cycles, ocp will be tripped. once ocp is tripped, both high side and low side mosfet will be turned off, and the internal discharge resistor at the vsen pin will be enabled to discharge output capacitors. ocp is a latched protection, it can only be reset by cycling vron or vcc. ocset v cc r oc1 r oc2
RT8153C/d 24 ds8153c/d-05 april 2011 www.richtek.com figure 14. thermal throttling setting principle over voltage protection (ovp) the ovp circuit is triggered under two conditions (without offset mode): ` condition 1 : when v vsen exceeds 1.7v. ` condition 2 : when v vsen exceeds v dac by 300mv (typ.). when offset mode, the relative over voltage protection is disable and the over circuit is triggered until v vsen exceeds 2v. if either condition is valid, the RT8153C/d latches the lgate = 1 and ugate = 0 as crowbar to the output voltage of vr. turning on all ls_fets can lead to very large reverse inductor current and potentially result in negative output voltage of vr. to prevent the cpu from damage by negative voltage. the RT8153C/d turns off all ls_fets when v vsen falls below ? 100mv. under voltage protection (uvp) if v vsen is lower than v dac by 400mv (typ.) a uvp fault will be tripped. once uvp is tripped, both high side and low side mosfet will be turned off and the internal discharge resistor at vsen pin will be enabled. uvp is a latched protection; it can only be reset by cycling vron or vcc. negative voltage protection (nvp) during the state when v vsen is lower than ? 100mv, the controller will force lgate = 0 and ugate = 0 to prevent negative voltage. once v vsen recovers to be higher than 0v, nvp will be suspended and lgate = 1 will be enabled again. over temperature protection (otp) over temperature protection prevents the vr from damage. otp is considered to be the final protection stage against overheating of the vr. the thermal throttling vrtt is set to be asserted prior to otp to manage the vr power. when this measure becomes insufficient to keep the die temperature of the controller below the otp threshold, otp will be asserted and latched. the die temperature of the controller is monitored internally by a temperature sensor. as a result of otp triggering, a soft shutdown will be launched and v vsen will be monitored. when v vsen is less than 200mv, the driver remains in high impedance state and the discharging resistor at vsen pin will be enabled. a reset can be executed by cycling vcc or vron. thermal throttling control intel imvp-6.5 technology supports thermal throttling of the processor to prevent catastrophic thermal damage. the RT8153C/d includes a thermal monitoring circuit to detect an exceeded user-defined temperature on a vr point. the thermal monitoring circuit senses the voltage change across ntc pin. figure 14 shows the principle of setting the temperature threshold. connect an external resistive voltage divider between vcc and gnd. this divider uses a negative temperature coefficient (ntc) thermistor and a resistor. the joint of the voltage divider is connected to the ntc pin in order to generate a voltage that is inversely proportional to temperature. the RT8153C/d pulls vrtt low if the voltage on the ntc pin is greater than 0.8 x v cc . the internal vrtt comparator has a hysteresis of 200mv (typ.) to prevent high frequency vrtt oscillation when the temperature is near the setting point. the minimum assertion/de-assertion time for vrtt toggling is 1.6ms (typ.). furthermore, this pin also provides load line enable/disable function in which the zero load line regulation can be implemented through ntc pin. the ntc pin will sink a 80 a current pulse inward the ic at vron rising edge and the ic will detect the voltage of ntc pin at the same time to determine whether the zero load line function is enabled or not. figure 15 is the recommended setting network of zero load line. the 100k ntc resistor is recommended in this setting network for zero load line application and the resistance of r1 is set to be the same value as the resistor at 25 c. in addition, the resistance of both r2 and r3 can be obtained by solving the equations 21 and 22. ntc + - + 0.8 x v cc vrtt cmp v cc ntc r tt
RT8153C/d 25 ds8153c/d-05 april 2011 www.richtek.com ntc ntcht ntc ntclt for 120 c r3 v x vcc 4v (r1/ /r ) r2 r3 for 20 c r3 v = x vcc 1.5v (r1 / /r ) r2 r3 == ++ ? = ++ (21) when dcr sensing network is used for ntc thermistor temperature compensation, the current monitor indication voltage, v cm , can be calculated as below : = load cm cm cmset 16 i dcr r k v r (25) to find r cm and r cmset follow below equation : = cm(max) cm cmset (max) cm v v r 16 i dcr r k (26) (22) current monitor figure 16 shows the current monitor setting principle. current monitor needs to meet imvp6.5 specification. the RT8153C/d is based on the relation between r droop and load current to provide an easy setting and high accuracy current monitor indicator. the current monitor indication voltage, v cm , is calculated as : = load cm cm cmset 16 i dcr r v r (23) where i load is the output load current, dcr is the load line setting of applications, and r cm and r cmset are the current monitor current setting resistors. to find r cm and r cmset , follow below equation : cm cm cmset (max) rv r 16 i dcr = (24) v cm must be kept equal to 1v and i (max) needs to follow the setting current of the imvp6.5 definition with various cpu. v cm is clamped not higher than 1.15v. for an example of current monitor setting, the following design parameters are given : figure15. for zero load line network i (max) = 30a, dcr = 1m , v cm = 1v, r cmset = 10k r cm = 20.8k ? where, k is dividing ration of dcr sensing. no load offset the RT8153C/d feature no-load offset function which provides the possibility of wide range positive/negative offset. the no-load offset function can be implemented through ofs pin. to enable no-load offset function, the voltage of the ofs pin should be higher than 0.9v at the vron raising edge. it is recommended to set the ofs pin at 1.2v before vron rising edge. the no-load offset range can be from 400mv to ? 200mv while ofs pin voltage varying from 1.6v to 1v. the output offset voltage magnitude is equaled to the voltage difference between ofs pin and the 1.2v. for example, the ofs pin should be set to 1.4v if the target offset voltage is 200mv and ofs pin should be set to 1.1v to have ? 100mv output offset voltage. the accuracy of this offset voltage is 10mv at no-offset point which ofs pin is 12v and the linearity of no-load offset function is higher than 95% in the 400mv figure 16. current monitor setting principle vsen v cc_sense current monitor generator r cmset cmset v cm r cm c1 rgnd cm ntc 0.8 x v cc r3 r2 r1 ntc vrtt cmp + - vcc
RT8153C/d 26 ds8153c/d-05 april 2011 www.richtek.com where t on is the ugate turn on period. higher inductance yields in less ripple current and hence in higher efficiency. the flaw is the slower transient response of the power stage to load transients. this might increase the need for more output capacitors driving the cost up. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the core must be large enough not to be saturated at the peak inductor current. output capacitor selection output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. usually, the cpu manufacturer recommends a capacitor configuration. two different kinds of output capacitors can be found including, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. latter ones are for mid- frequency decoupling with especially small esr and esl values while the bulk capacitors have to provide enough stored energy to overcome the low frequency bandwidth gap between the regulator and the cpu. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT8153C/d, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-32l 4x4 packages, the thermal resistance, ja , is 52 c/w on a standard jedec 51-7 four-layer thermal test board. for wqfn-32l 5x5 packages, the thermal resistance, ja , is 36 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (36 c/w) = 2.778w for wqfn-32l 5x5 package p d(max) = (125 c ? 25 c) / (52 c/w) = 1.923w for wqfn-32l 4x4 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for the RT8153C/d packages, the derating curves in figure 17 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 17. derating curve for RT8153C/d package 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four layers pcb wqfn-32l 5x5 wqfn-32l 4x4 ? ? = in out (min) on ripple max vv lt i (27) to ? 200mv range. furthermore, the offset function has clamp mechanism to prevent the output voltage run-away. the lower limit of the offset function is ? 300mv which means the output offset voltage magnitude will keep exactly ? 300mv even if the ofs pin voltage is lower than 0.9v. in another hand, the upper limit of the offset function is about 600mv which means the output offset voltage magnitude will keep about 600mv even if the ofs pin voltage is higher than 1.8v. inductor selection the switching frequency and ripple current determine the inductor value as follows :
RT8153C/d 27 ds8153c/d-05 april 2011 www.richtek.com layout considerations careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for optimum pc board layout : ` keep the high current paths short, especially at the ground terminals. ` keep the power traces and load connections short. this is essential for high efficiency. ` the slew rate control capacitor should be connected from soft to rgnd. ` when trade-offs in trace lengths must be ma de, it?s preferable to allow the inductor charging path to be made longer than the discharging path. ` place the current sense component close to the controller. isen and isen_n connections for current limit and voltage positioning must be made using kelvin sense connections to guarantee the current sense accuracy. the pcb trace from the sense nodes to controller should be parallel to each other. ` route high-speed switching nodes away from sensitive analog areas (soft, comp, fb, vsen, isen, isen_n, cm, etc...)
RT8153C/d 28 ds8153c/d-05 april 2011 www.richtek.com outline dimension e d 1 d2 e2 l b e a a1 a3 see detail a note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 4.950 5.050 0.195 0.199 d2 3.400 3.750 0.134 0.148 e 4.950 5.050 0.195 0.199 e2 3.400 3.750 0.134 0.148 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 32l qfn 5x5 package
RT8153C/d 29 ds8153c/d-05 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 3.900 4.100 0.154 0.161 d2 2.650 2.750 0.104 0.108 e 3.900 4.100 0.154 0.161 e2 2.650 2.750 0.104 0.108 e 0.400 0.016 l 0.300 0.400 0.012 0.016 w-type 32l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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